1. Field of the Invention.
This invention relates to a semiconductor device, and more particularly, to a semiconductor device which features imprements in the electrodes and wiring structures used in the formation of the insulated gate field-effect transistors incorporated in the device.
2. Description of the Related Art.
User demand has made it necessary to develop semiconductor devices and particularly elements constituting integrated circuits which can be formed at a high integration density and can operate at high speed. Three types of conventional insulated gate field-effect transistors (hereinafter referred to as MOS transistors) currently used as the above elements will now be explained, with reference to FIG. 3.
In FIG. 3, P.sup.+ -type drain region 2 and P.sup.+ -type source region 3 are formed in the surface area of N-type semiconductor substrate 1. Gate electrode 4 and channel region 5, also formed in the surface area of substrate 1, are arranged such that they oppose each other, with a gate insulation film 6, 100 to 500 .ANG. in thickness, interposed therebetween. Elements 1 to 6 are the basic parts which make up P-channel MOS transistor 10. In order that the device have electrically stable characteristics, it is essential that gate insulation film (SiO.sub.2) 6 be protected against external contamination.
To this end, field oxide film 7 is formed for element isolation, and CVD-SiO.sub.2 film 8 is deposited thereon as a protection film. Wiring layers 9 and 11 are formed such that they are connected to the drain and source regions.
In the above MOS transistor, gate electrode 4 is often formed of polycrystalline silicon. Polysilicon gate electrode 4 can be used as a mask when P.sup.+ -type drain and source regions 2 and 3 are formed in a self-alignment process. Moreover, after formation of gate electrode 4, it can be heat-treated at high temperature for activation. With the enhancement of the integration density and operation speed of the integrated circuit using the MOS transistor, it has been strongly required to reduce the resistance of the electrode and wiring sections of the element.
When used as material for the gate electrode, the polysilicon layer exhibits the preferable characteristics. However, even if an impurity is doped in the polysilicon layer at a high impurity concentration by use of a thermal diffusion technique, the resistivity thereof cannot be set lower than 3.times.10.sup.-3 to 5.times.10.sup.-3 .OMEGA..multidot.cm. As a result, the high speed operation of minute elements is restricted by a low-pass filter formed by the resistance of the electrode wiring section and the capacitance associated with the wiring.
For the reasons described above, it is now common practice to use, in place of the polysilicon layer, metal or metal silicide having a lower resistance, or to use a laminated structure composed of the polysilicon layer and a single- or multi-layered metal silicide, in order to form the gate electrode (which is disclosed in, for example, Japanese Patent Publication No. 48-13583).
In the case where a metal gate electrode is used, the metal gate electrode may tend to react with a silicon film or with a film for insulating layers during a heat treatment process. Therefore, after the formation of the metal gate electrode, the succeeding processes must be effected at low temperature, thus limiting the applicability of the device. In the case where metal silicide is used, silicide of Pt, Ti, Mo, W, Ta or the like can be used. In particular, titanium silicide is used because of its low resistance.
However, in the case where titanium silicide is directly used, the same problem as in the case of using metal will occur.
Further, in the case where a titanium silicide layer is directly formed on a polysilicon film having phosphorus doped therein, leakage current in gate oxide film 6 increases, degrading the voltage withstanding characteristics thereof. The reason for this is considered that the grain size of polysilicon increases because of phosphorus which has been thermally diffused into the polysilicon film, and the grain boundary may be formed from the upper side to the lower side of the polysilicon film, permitting titanium to react with the gate oxide film via the boundary and thus increasing the leakage current. The diffusion of titanium is considered to occur in a heat treatment process at high temperature effected immediately after the titanium silicide is formed.
FIG. 4 shows the withstanding voltage characteristics in the case where polysilicon is used as material for the gate electrode. The abscissa indicates the electric field strength applied to the gate oxide film in mega volt for 1 cm thickness, and the ordinate indicates the number of tested gate oxide films which break down at the tested electric field strength.
The test for the withstanding voltage characteristic has been effected by stepwisely increasing a test voltage of 0.5 MV/cm while keeping the stepped voltage for 0.2 sec until a predetermined leak current flows.
As is clearly seen from FIG. 4, when the gate electrode is formed by depositing a titanium silicide layer on a polysilicon film having phosphorus doped therein, the withstanding voltage of the gate oxide film is lowered and variation in the withstanding voltage becomes large. Such deterioration of the withstanding voltage lowers the yield and reliability of LSIs.